1. Field of the Invention
The present invention relates to an amplifying circuit of an amplifier, and more particularly, to an amplifier which is driven in a complementary manner using a common source amplifying circuit to extend the input and output signal voltage range.
2. Description of the Prior Art
The rapid growth of technology has insured that electronic signals will remain an important medium for transmitting data. Signals are used to control various servers, mechanical devices, and electrical apparatus. They allow people to control many fast and labor-saving machines, adding convenience to modern life. Of course, electronic signals are also an indispensable medium for data transmission. Things we often take for granted, such as mobile phones, radio, television, and satellite communications, all rely on electronic signals.
Good circuit design is indispensable for processing these electronic signals and amplifiers are often foundation blocks for circuits. Base functions of an amplifier are to amplify or magnify the signal, and to provide buffering and driving capability. Although the electric driving ability (including current and/or voltage) of the electronic signal is not large, the amplifier can be driven and also generate output signals which have a larger electric driving ability, or current strength, and maintain the same waveform as the input signals.
Please refer to FIG. 1. FIG. 1 is a functional block diagram of a prior art amplifier 10. The amplifier 10 comprises an input circuit 12, an output circuit 14, and a unit-gain buffer circuit 18 connected between the input circuit 12 and the output circuit 14. The input circuit 12 is used to receive signals transmitted from an external circuit (not shown in FIG. 1). After the signals have passed through the input circuit 12, the signals travel to an input end of the unit-gain buffer circuit 18. The input end is connected to a node A. The unit-gain buffer circuit 18 will not amplify voltage amplitude of the signals (so it is unit-gain), but it can provide an input signal buffer and increase the strength of the current. That means, although the current driving ability of the signals transmitted into the unit-gain buffer circuit 18 is not large, the unit-gain buffer circuit 18 can be driven and also generate output signals which have a larger current while having the same voltage amplitude as the input signals. The output signals transmit to the output circuit 14 through a node B. The output circuit 14 can further amplify the signals, and provide good output impedance.
A typical unit-gain buffer circuit is composed of an operational amplifier and a suitable negative feedback circuit. The unit-gain buffer circuit 18 shown in FIG. 1 uses the operational amplifier 16 to be a main portion of the unit-gain buffer circuit 18. The operational amplifier 16 has two differential input ends; one of the input ends is connected to node A, and another input end is connected to an output end of the operational amplifier in node B through an electrical path 19, forming the negative feedback circuit.
In theory, the voltage waveform of the signals on node B (the output end of the unit-gain buffer circuit 18) is the same as the voltage waveform of the signals on node A (the input end of the unit-gain buffer circuit 18), achieving a result of unit-gain. The functional relationship between the input signal voltage and the output signal voltage in an ideal unit-gain buffer circuit is perfectly linear. However, this is not possible in the real world. Because the operational amplifier has certain output voltage swing limitations, the output signal voltage of the unit-gain buffer circuit also has certain voltage swing limitations. Particularly, when the input signal voltage of the unit-gain buffer circuit becomes small (near zero voltage), because of the lower limit of the voltage range of the output signal, the output signal voltage of the unit-gain buffer circuit is unable to follow the low input signal voltage. Therefore, the error between the output signal voltage and the input signal voltage will increase, and the unit-gain buffer circuit cannot achieve the function of unit-gain. Similarly, when the input signal voltage of the unit-gain buffer circuit becomes large, near current bias of the amplifier, because of the upper limit of the voltage range of the output signal, the output signal voltage of the unit-gain buffer circuit is also unable to follow the input signal voltage. Therefore, the unit-gain buffer circuit cannot achieve the ideal unit-gain standard.
For a further description of the limitations of the output signal voltage range of an actual unit-gain buffer circuit, please refer to FIG. 2. FIG. 2 is a perspective view of an amplifying circuit 20 according to a prior art. Besides a typical input circuit 22 and an output circuit 24, the amplifying circuit 20 uses a gain circuit 26 to be the unit-gain buffer circuit. VDD is used for biasing the gain circuit 26. The gain circuit 26 comprises a first differential pair 28, a second differential pair 30, a first driving circuit 32 and a second driving circuit 34. Two differential ends of the first differential pair 28 are connected to nodes NN1 and NN2. Two differential ends of the second differential pair 30 are also connected to nodes NN1 and NN2. The first differential pair 28 is connected to the first driving circuit 32 on nodes NN4 and NN5 in a cascade manner. The second differential pair 30 is also connected to the second driving circuit 34 on nodes NN6 and NN7 in a cascade manner. The first driving circuit 32 is connected to the second driving circuit 34 on nodes NN8 and NN3. Node NN3 is used as an output end of the gain circuit 26. Nodes NN1 and NN2 are used as two differential input ends of the operational amplifier. Node NN1 is an input end of the gain circuit 26. Node NN2 is connected to node NN3 through path 29, forming a negative feedback circuit and making the gain circuit 26 a unit-gain buffer circuit.
In the gain circuit 26, the first differential pair 28 comprises two n-type MOS (metal-oxide semiconductor) transistors M1 and M2. The first differential pair 28 is biased by current source Iss1. The second differential pair 30 comprises two p-type MOS transistors MP1 and MP2. The second differential pair 30 is biased by current source Iss2. Two output ends of the first differential pair 28 are connected to nodes NN4 and NN5, and use transistors M9 and M10 to be active load. Gates of transistors M9 and M10 use direct current voltage Vg4 to bias. The transistors M9 and M10 are used as a current source. Gates of the two transistors M3 and M4 in the first driving circuit 32 use direct current voltage Vg3 to bias, making the transistors M3 and M4 function as a common-gate amplifier. Similarly, in the second driving circuit 34, the transistors M5 and M6, biased by direct current voltage Vg2, are also used as a common-gate amplifier. The transistors M7 and M8 form a current mirror for biasing and to be active load.
The operation of the prior art gain circuit 26 can be described as follows. The nodes NN1 and NN2 can be treated as two differential input ends of the first differential pair 28 and the second differential pair 30. The signals inputted into the two differential input ends of the first differential pair 28 will output to the active load M9 and M10 through nodes NN4 and NN5, and be amplified by transistors M3 and M4 that are common-gate amplifiers. Then the signals will be outputted to nodes NN8 and NN3. On the other side, the signals inputted into the two differential input ends of the second differential pair 30 will be outputted to nodes NN6 and NN7. The transistors M7 and M8 that form the current mirror, can couple the signals (including the contribution of the transistors M3 and M5 of the common-gate amplifier) on node NN8 to node NN7 through the transistor M8, by way of the common-gate amplifier of the transistor M6. The dual end signals inputted to nodes NN1 and NN2 can be changed to one end output on node NN3. The electricity path 29 between node NN2 (one of the differential input ends) and node NN3 (the output end of the gain circuit 26) forms a negative feedback circuit, making the prior art gain circuit 26 a unit-gain buffer circuit.
The drawback of the gain circuit 26 in the prior art amplifier 20 is that the common-gate amplifiers (that are transistors M3, M4, M7 and M8) are connected in a cascade manner. This design increases the limitations on the input signal voltage on node NN3, causing the output signal voltage range on node NN3 to become correspondingly smaller. The output signal voltage is unable to go down to near zero voltage and unable to rise up to near VDD voltage. Because the common-gate amplifiers of the prior art gain circuit 26 are connected in a cascade manner, the lower limit of the output signal voltage range on node NN3 of the prior art gain circuit 26 will be affected by voltage across the transistors M6 and M8 (voltage between source-drain of the transistors M6 and M8). If the voltage across the transistors M6 and M8 is too small, the operation point of the transistors M6 and M8 will be driven into triode region, making the transistors M6 and M8 unable to operate normally. To maintain the normal operation voltage across the transistors M6 and M8, the lower limit of the output signal voltage range on node NN3 cannot be near zero voltage (voltage of ground). Similarly, because the common-gate amplifier (transistor M4) of the first driving circuit 32 is connected in a cascade manner, the upper limit of the output signal voltage range on node NN3 will be affected by normal voltage across the transistors M4 and M10. If the voltage (voltage between source-drain of the transistors M4 and M10) across the transistors M4 and M10 is too small, the operation point of the transistors M4 and M10 will be driven into triode region, making transistors M4 and M10 unable to operate normally. To make the transistors M4 and M10 operate normally, the upper limit of the output signal voltage range on node NN3 cannot be near the direct current voltage VDD. The reasons mentioned above make the output signal voltage range on node NN3 in the prior art gain circuit 26 unable to fully extend from zero voltage to VDD. If an input signal voltage to node NN1 of the gain circuit 26 (which is used as a unit-gain buffer circuit) is too small (near zero voltage) or too large (near VDD), the output signal voltage of the gain circuit 26 is unable to follow the input signal voltage correctly because of the limitations of the output signal voltage range on node NN3. Therefore, there is a non-linear functional relationship between the input and output signal, making the prior art amplifier 20 unable to operate normally.
In order to increase the usefulness of integrated circuits, decrease power consumption, and avoid complex circuit designs and non-desirable effects of semiconductor elements, today""s circuits use positive direct current voltage (such as the direct current voltage VDD mentioned above) to bias. It is better if the voltage of the direct current is smaller. Therefore, the normal operation range of the amplifier is stricter. It is good if the input and output signal voltage range of the amplifier can be extended fully from zero to direct current voltage VDD and the amplifier operates normally in that range. One of the functions of the unit-gain buffer circuit is to make the output signal voltage follow the input signal voltage (unit-gain). One method of measuring the operation of the unit-gain buffer circuit is to measure the error between the input and output signal voltage. If the input signal voltage is as low as 0.3 volts, the designer of the unit-gain buffer circuit hopes that the error between the input and output signal voltage is less than several ten microvolts. Similarly, if the input signal voltage is between VDD and 0.3 volts (meaning the input signal is within 0.3 volts of the VDD), the designer hopes that the error between the input and output signal voltage is less than several ten microvolts. However, because the common-gate amplifiers of the gain circuit 26 (which is treated as the unit-gain buffer circuit) shown in FIG. 2 are connected in a cascade manner, when the input signal voltage is less than 0.3 volts or greater than VDD-0.3 volts, the error between the input and output signal voltage is greater than one hundred microvolts. This great error is a serious limitation of gain circuit 26.
It is therefore a primary objective of the claimed invention to provide an amplifier that is driven in a complementary manner, using a common source amplifying circuit to extend the input and output signal voltage range.
The amplifier according to the claimed invention includes a push-up circuit and a pull-down circuit. The push-up circuit includes a first differential pair and a first driving circuit. The first driving circuit is connected to the first differential pair in a cascading manner. The first driving circuit has a common source amplifying circuit formed of a MOS (metal-oxide-semiconductor). The pull-down circuit includes a second differential pair and a second driving circuit. The second driving circuit is connected to the second differential pair in a cascading manner. The second driving circuit has a common source amplifying circuit formed of a MOS. A portion of a normal operation voltage range of the push-up circuit overlaps a portion of a normal operation voltage range of the pull-down circuit. A remaining portion of the normal operation voltage range of the push-up circuit falls outside the normal operation voltage range of the pull-down circuit. A remaining portion of the normal operation voltage range of the pull-down circuit falls outside the normal operation voltage range of the push-up circuit.
It is an advantage of the claimed invention that the first and second driving circuit is connected to the first and second differential pair in a cascading manner. Therefore, although the input signal voltage is extremely small or extremely large, the output signal voltage can follow the input signal voltage, effectively improving on the non-linear phenomenon in the prior art.
These and other objectives of the claimed invention will be apparent to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings. dr
FIG. 1 is a functional block diagram of an amplifier according to a prior art.
FIG. 2 is a perspective view of an amplifying circuit according to a prior art.
FIG. 3 is a circuit structural diagram of an amplifier according to the present invention.